1. Field of the Invention
This invention relates generally to semiconductor device fabrication and to an interconnect module having one or more signal planes, each containing a high density of interconnecting signal lines. More particularly, the present invention relates to a method and apparatus for selectively disconnecting and/or connecting predetermined areas on multilayered interconnect modules including areas below the surface of the device.
2. Description of the Prior Art
Although modern semiconductor devices have greatly increased in speed, the increased speed of computer systems has been limited by the signal propagation delay between the semiconductor devices. The cycle time in a computer system is proportional to approximately equal contributions from the semiconductor devices and the signal propagation, or package delay. Improvements in semiconductor devices have lowered the cycle times and now attention is directed to reducing the signal propagation delay in order to further increase computer system speeds. Presently, cycle times are approximately 70 nsec., however a 2 to 4 nsec. range is considered attainable.
Present day printed wiring boards may have dimensions of about 20".times.20", thus a reduction in dimensions, to approximately 4".times.4", would greatly reduce the system's signal propagation delay, and therefore reduce cycle time. Obviously, to reduce the size of the wiring boards, it is necessary to pack the semiconductor devices closer to each other by mounting the semiconductor chips on a multichip interconnect module having a very large density of signal lines.
This has been partially accomplished by using the thin film technology described by C. W. Ho, et al. in IBM J. Res. Develop., 26, 286 (1982). Ho et al. disclosed that, in order to satisfy the electrical requirements of propagation of high speed pulses on thin film transmission lines while preserving the required high wiring density, it is necessary to build signal lines with high aspect ratios, i.e., a large line thickness to line width ratio. For example, the width of the signal line may be 8-microns wide and the height may be 6 to 8 microns high, yielding an aspect ratio of 0.75 to 1.0. However, as pointed out by Ho et al., it is extremely difficult to build high density thin film signal lines having an aspect ratio approaching or greater than 1.0.
Subsequently, Jensen et al. in IEEE Transactions on Components Hybrids and Manufacturing Technology, Vol. CHMT-7, 384 (1984) demonstrated that it is possible to achieve an acceptable degree of planarization and build a two-layer thin film module by first depositing the metal signal layer, then applying very thick dielectric polyimide films. Because thin coats of polyimide films do not produce the necessary planarity, a thick polyimide film is required. Furthermore, the wiring density is relatively low, approximately 80 lines/cm/signal layer. Other disadvantages of the Jensen et al. approach include a potential of impedance control due to variation in the polyimide thickness, difficulty in interconnecting signal wires, or adjacent signal layers and the need for several additional manufacturing steps. More recently, researchers have shown that, by using electroplating techniques, it is possible to build lines with a wiring density of 400 lines/cm/signal layer.
In a typical electroplating technique, a thin plating base, consisting of a patterned metal film is first deposited onto the substrate. Subsequently, a several micron thick dielectric film is deposited on top of the plating base. By either a photolithographic technique or by a conventional etching technique, the dielectric film over the plating base is selectively removed. The substrate is then placed in a plating bath, and a thick metal film is plated over the plating base to a thickness essentially the same as the thickness of the surrounding dielectric film. Thus, a planar surface is formed. This planar configuration permits the fabrication of a second signal layer on top of the first signal layer without the problem of step coverage that can occur when lines cross devices or other lines below them. Planarization effectively avoids the problems inherent in step coverage.
While the electroplating method has several advantages, it suffers a very serious limitation. The signal lines must be completely interconnected for the electroplating process to proceed. This limitation can be partially overcome by connecting all the signal lines at one or both ends of the substrate and cutting the interconnect area after the manufacture of the thin film module is completed. However, this technique does not permit an isolated signal line away from the edge of the substrate to be formed, thus posing potentially unacceptable constraint in the design of multilayered interconnect modules.
Also, in present semiconductor device fabrication technology, it is often necessary to utilize redundancy in order to improve fabrication yields as device density increases. In such semiconductor chips, redundant devices are fabricated, and if a device or a portion of a chip is nonfunctional, a laser beam is used to cut the conductors on the surface of the semiconductor chip leading to the nonfunctional portion in order to isolate that portion from the properly functioning devices. This technique is called laser ablation and is now commonly used by semiconductor chip manufacturers when manufacturing large scale devices, such as, for example, 256K memory devices; however, the technique is usable only for breaking connections on the surface of a device and cannot be used to break connections below the surface without causing damage to the surrounding area. Neither does it provide for a method to connect two signal wires without an elaborate scheme involving highly toxic metal organic gaseous compounds.